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PowerQUICC II Register Programming
Table 6-6. Memory Controller Initialization For 100MHz—Flash as Boot Device
Reg.
BR1
Device Type
BCSR
Bus
PPC
Init Value
[hex]
04501801
Description
Base at 04500000, 32 bit port size, no parity,
GPCM
OR1
FFFF8010
32 KByte block size, all types access, 1 w.s.
BR2
OR2
SDRAM
MT48LC4M32B2
MICRON
by
PPC
00000041
FE002EC0
Base at 0, 64 bit port size, no parity, SDRAM
machine 1
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
BR4
E 2 PROM
PPC
C2000801
Base at C2000000, 8 bit port size, write protect
disabled, no parity, GPCM
OR4
AT28HC64B-70JC
by
FFFF8866
32 KByte block size, CS output half a clock after
Atmel
address, all types access, 6 w.s., Timing relax
BR5
PM5384 - ATM UNI
PPC
04600801
Base at 04600000, 8 bit port size, no parity, GPCM
on PPC bus.
OR5
FFFF8E56
32K Byte block size, delayed CS assertion, early
CS and WE negation for write cycle, relaxed
timing, 7 w.s. for read, 8 for write, extended hold
time after read.
BR3
PCI Interrupt Controller
PPC
04731801
Base at 04730000, 32 bit port size, no parity,
GPCM on PPC bus.
OR3
FFFF8010
32 KByte block size, all types access, 1 w.s.
Table 6-7. Memory Controller Initialization For 100MHz—E 2 PROM as Boot Device
Reg.
BR0
Device Type
E 2 PROM
Bus
PPC
Init Value
[hex]
FFF00801
Description
Base at FFFFE000, 8 bit port size, write protect
disabled, no parity, GPCM
OR0
AT28HC64B-70JC
by
FFFF8866
32 KByte block size, CS output half a clock after
Atmel
address, all types access, 6 w.s., Timing relax
BR1
BCSR
PPC
04501801
Base at 04500000, 32 bit port size, no parity,
GPCM
OR1
FFFF8010
32 KByte block size, all types access, 1 w.s.
BR2
OR2
SDRAM
MT48LC8M16A2
MICRON
by
PPC
00000041
FE002EC0
Base at 0, 64 bit port size, no parity, SDRAM
machine 1
32MByte block size, 4 banks per device, row starts
at A7, 12 row lines, internal bank interleaving
allowed, normal AACK operation
MPC8272ADS User Guide
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